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Jun 23 2018

Supercomputing at Fujitsu: Post-K System and CPU Prototypes at ISC High Performance 2018


Fujitsu has developed and produced the prototype of an ARM processor that is supposed to power the so-called Post-K System, the direct successor to the company's famous K computer.

Just like the older supercomputer (pictured above), the Post-K System is a collaborative effort by Fujitsu Ltd., the company's Japanese headquarters, and the RIKEN Center for Computational Science (R-CCS), a branch of the country's largest comprehensive research institution. Post-K is expected to take up full operations in 2021; right now, however, the developers are still working on a new main processor that will replace the predecessor's SPARC64 VIIIfx CPUs.

According to the official press release – whose respective versions can be found here and here – the new processor design will be based on the 64-bit ARMv8-A SVE microarchitecture. In this context, SVE stands for "Scalable Vector Extension," an instruction set intended to notably improve the vector processing capabilities of HPC systems, to which Fujitsu has made substantial contributions. The finished version of the CPU will feature a total of 48 cores plus two or four "assistant cores," depending on the type of node they're used in, which can either be of sole "computational" or mixed "I/O and computational" breed. As Fujitsu tells it, each node will be equipped with a single CPU, but operators shall be able to stuff up to 384 nodes into one rack, allowing for a theoretical maximum of 18,432 processor cores (plus extra helper cores) per rack that in turn could help R-CCS to reach new levels of compute density. The nodes talk to each other via Fujitsu's third-generation, "6D mesh" Torus fusion (Tofu) interconnect, which will likely offer much higher internal data transfer rates than the bi-directional 125 GB/s that can be drawn from today's Tofu2 links. Functionality trials are about to commence as soon as possible.

Like other HPC solutions, e.g. from Cray, IBM or various Chinese HPC outfits, the Post-K System will also be loaded with a customized software package, in this case a combination of an RHEL-based Linux and a lightweight McKernel variant that serves as the OS, the Fujitsu Exabyte File System (FEFS), successors to the Fujitsu Software Technical Computing Suite and Fujitsu Software Technical Computing Language, and lastly the FDPS library framework, which was created to support developing particle simulators. Next to being used in HPC scenarios, the Post-K System with its support for half-precision and double-precision arithmetic also looks poised to tackle new tasks in areas like AI, ML/DL (machine learning/deep learning), and simulation. Other focus areas include healthcare, risk prevention and mitigation in the face of natural disasters, climate modelling, and the development of clean energy systems. In terms of sheer execution power, Post-K is supposed to deliver up to 100 times the performance of the K computer, whereas power consumption would only increase three- to fourfold to somewhere between 30 and 40 megawatts. Based on the above characteristics, Post-K would not only be a solid contender among the yet-to-emerge "exascale systems" that are currently expected to dominate the TOP500 list of supercomputers from 2020 onwards, but also rank highly among the world's most energy-efficient HPC installations.

Prototypes of the Post-K System and its ARM-based processing unit will be on display at this week's ISC High Performance 2018 exhibition in Frankfurt, Germany, which started on Sunday and runs until Thursday (June 28). For more details and background info, please refer to RIKEN's project microsite, Fujitsu's "Hot Chips 28" presentation, and the in-depth report over at The Next Platform (author: Timothy Prickett Morgan). Or if you're more of a visual type, just check out the video below (courtesy of RIKEN):


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